1. Field of the Invention
The present invention relates to a display device, and more particularly, to a technology effectively applied to a display device including a top gate TFT element using a polycrystalline semiconductor.
2. Description of the Related Art
An example of a display device including a TFT element having a MIS structure (including MOS structure) is an active matrix TFT liquid crystal display device.
The active matrix TFT liquid crystal display device includes a TFT liquid crystal display panel in which a liquid crystal material is sealingly filled between two substrates. One of the two substrates (hereinafter, referred to as TFT substrate) has a display area in which TFT elements used as active elements (hereinafter, sometime referred to as switching elements) are arranged in matrix.
Up to now, in many cases, each of the TFT elements used as the active elements in the TFT substrate has a semiconductor layer made of an amorphous semiconductor such as amorphous silicon (a-Si). However, in recent years, the semiconductor layer of the TFT element used as the active element in a TFT liquid crystal display device is made of, for example, a polycrystalline semiconductor such as polycrystalline silicon (poly-Si).
In a conventional normal TFT liquid crystal display device, driver circuits (integrated circuits) such as a gate driver for generating and controlling scanning signals supplied to scanning signal lines (hereinafter, sometime referred to as scanning driver) and a data driver for generating and controlling video signals supplied to video signal lines are mounted as chip parts (driver ICs) separately from the liquid crystal display panel. However, in recent years, for example, the TFT liquid crystal display device includes the driver circuits such as the gate driver and the data driver which are provided outside the display area of the TFT substrate.
The driver circuits such as the gate driver and the data driver should be operated at higher speed than the active elements in the display area. Therefore, when the driver circuits are to be provided outside the display area of the TFT substrate, the driver circuits desirably include TFT elements using the polycrystalline semiconductor.
The polycrystalline semiconductor used for the TFT element of a semiconductor device such as the TFT liquid crystal display device is, for example, low-temperature polycrystalline silicon (LTPS) in many cases. When the low-temperature polycrystalline silicon is to be formed, for example, an amorphous silicon film is formed on a surface of an insulating substrate and crystallized after being melted. Therefore, when the TFT element using the low-temperature polycrystalline silicon is to be formed, a semiconductor layer (low-temperature polycrystalline silicon layer), a gate insulating film, and a gate electrode are formed in the stated order on the insulating substrate in many cases. The TFT element in which the gate electrode is laminated above the semiconductor layer as viewed from the insulating substrate side is called a top gate TFT element.
In the case of the top gate TFT element, for example, the semiconductor layer, the gate insulating film, and the gate electrode are formed. After that, impurities are implanted into the semiconductor layer using the gate electrode as a mask to form a source diffusion region and a drain diffusion region. In such a manufacturing method, the gate electrode and the semiconductor layer should be crossed in order to separate the source diffusion region and the drain diffusion region from each other.
However, when the gate electrode crosses the semiconductor layer in the top gate TFT element using the LTPS, for example, there is a problem in that a conduction current or an on-resistance varies while the TFT element is in a conductive state (on-state). The problem is remarkable, for example, in the case of a TFT element having a reduced gate width (channel width).
When the gate electrode crosses the semiconductor layer in the top gate TFT element using the LTPS, for example, there is a problem in that a leak current flows between a source and a drain while the TFT element is in a non-conductive state (off-state).
In recent years, in order to solve, of the two problems described above, the problem that the leak current flows between the source and the drain, for example, some methods of changing a two-dimensional shape of the TFT element into a shape in which the leak current is prevented from easily flowing have been proposed (see, for example, JP 07-326764 A and JP 08-160469 A).
As described above, the semiconductor device including the top gate TFT element using the LTPS has the problem that the conduction current or the on-resistance easily varies while the TFT element is in the conductive state and the problem that the leak current flows while the TFT element is in the non-conductive state.
One of the reasons why the leak current flows between the source and the drain while the top gate TFT element using the LTPS is in the non-conductive state (off-state) is as follows. That is, the action of an electric field directed from the gate electrode to edge portions (portions close to etching end surfaces) of a region of the semiconductor layer which overlaps with the gate electrode (hereinafter, sometime referred to as channel region) are different from the action of an electric field directed from the gate electrode to a central portion of the region of the semiconductor layer.
Therefore, in the case of the TFT element described in JP 07-326764 A, for example, a gate length (hereinafter, sometime referred to as channel length) of each of both sides (edge portions) parallel to a direction in which the current flows, of the region of the semiconductor layer which overlaps with the gate electrode (hereinafter, sometime referred to as channel region) is set to a value larger than a gate length of the central portion. Thus, the leak current is prevented from flowing between the source and the drain.
In the case of the TFT element described in JP 08-160469 A, for example, the gate electrode is formed into a ring shape to eliminate the edge portions parallel to the direction in which the current flows, from the region of the semiconductor layer which overlaps with the gate electrode. Therefore, the leak current is prevented from flowing between the source and the drain.